The semiconductor industry has moved to using copper in various aspects of semiconductor devices due to certain advantages of copper over other metals. Copper has a first advantage of having lower resistivity than, for example, aluminum. As a result, copper circuitry suffers less from resistance-capacitance (RC) delays. This makes copper systems faster. Further, copper has increased resistance to electromigration, thereby enabling smaller scaling of semiconductor devices. However, with increased use, certain problems particular to copper have become more prevalent. One such problem is that copper has a high diffusivity through dielectric and silicon materials on which the copper is deposited. This is especially the case for so-called low-K dielectric materials, which are coming into increasingly common usage. This is problematic because the presence of copper in these materials may “poison” the materials and lead to semiconductor device failure.
In conventional methodologies, a barrier material is typically deposited on the dielectric material between the copper layer and the dielectric (or silicon) material, thereby preventing the copper from diffusing into the dielectric or silicon material. Typically, tantalum (Ta) or titanium (Ti) based barrier materials (e.g., tantalum nitrides (TaN), tantalum silicon nitrides (TaSiN), or titanium nitrides (TiN)) are used as barrier layers for copper. However, such materials also have limitations. For example, they can have porous boundaries which create a diffusion path for copper. Additionally, the thickness of existing barrier layers create some difficulties as feature size decreases. This is especially true as feature sizes decrease below 0.35 micron (μ).
A conventional prior art process for creating a copper interconnect is described hereinbelow with respect to FIGS. 1-5. In FIG. 1, a typical semiconductor wafer 100 is placed in a process chamber 101 and various layers of material and circuit structures are formed thereon.
FIG. 2 is a cross-sectional view of an active device and first metal layer of a semiconductor device formed on the wafer (or substrate) 100 of FIG. 1. In FIG. 2, the substrate 100, typically silicon, has an active device 110 formed thereon. The active device 110 has a gate region 120 on the substrate 100, and a source region 130 and a drain region 140 in the substrate 100. The active device 110 is fabricated using conventional techniques known to one skilled in the art. A first insulating layer 150 is formed over the gate region 120 and down to the substrate 100, over the source region 130 and drain region 140. The first insulating layer is typically silicon dioxide; however, combinations of silicon dioxide and other doped dielectrics (e.g. BPSG, PSG) are also commonly used. FIG. 2 shows an opening 160 which has been formed in the first insulating layer 150 and subsequently filled with a metal-containing material such as tungsten. Other material including, but not limited to, copper and aluminum may also be used. The opening 160 has been depicted as a via, but other openings including, but not limited to, trenches and inter-level interconnect structures may also be used. A metallization layer 170 is deposited over the first insulating layer 150 and the first opening 160. The metallization layer 170 is typically copper, but may also be aluminum or tungsten. After the metallization layer 170 has been formed, material is removed to leave a metal plug 170 over the filled opening 160. This structure is then treated to form copper interconnects.
FIG. 3 shows the topmost portion of FIG. 2. In particular, the plug 170 is shown. An insulating layer 180 of low-K dielectric material is formed over the entire surface, including the plug 170. Then the region over the plug 170 is etched away to define a trench 171. Then, a barrier layer 190 is formed over the surface, including the trench 171. Such a barrier layer 190 is typically formed of TaN or other Ta containing barrier materials or TiN barrier materials. Typically, the barrier layer 190 is formed using PVD techniques. After forming the barrier layer 190, a copper seed layer 191 is formed over the barrier layer 190. The seed layer provides a conductive surface for use in subsequent bulk copper deposition, which is typically performed by electroplating. With reference to FIG. 4, a bulk copper layer 192 (which fills in the trench 171) is formed on copper seed layer 191. Such bulk copper layers 192 are often formed using electroplating, but other deposition techniques are also possible, as known to those of skill in the art. Further processing, for example chemical mechanical polishing (CMP), can be used to planarize the surface, as is shown in FIG. 5. The bulk copper layer 192 can also be sealed by the deposition of another layer of a barrier material.
For the reasons described hereinabove, as well as other reasons, an improved method of forming barrier layers for copper is needed.